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Synopsys Introduces HDL Rule Checking for Altera System-On-a-Programmable-Chip Design Flow
MOUNTAIN VIEW, Calif.----Oct. 26, 2000--
Synopsys Inc. (Nasdaq:SNPS), the technology leader for complex
integrated circuit (IC) design, today announced availability of the
Altera® Coding Style 1.0 policy for Synopsys' LEDA® family of
hardware description language (HDL) checkers.
The policy is a source file that is used to configure the LEDA
checkers. It contains critical Verilog and VHDL coding-style rules to
minimize design flow bottlenecks and optimize quality of results (QoR)
for system-on-a-programmable-chip (SOPC) development using Altera
programmable logic devices (PLDs) with design-tools such as Synopsys'
FPGA Compiler II and FPGA Express.
``Being able to automatically ensure optimal coding-styles for
Altera devices and design flows offers tremendous advantages for
customers working with our million-gate APEX(TM) PLDs and our
Excalibur(TM) embedded processor solutions,'' said David Greenfield,
director of development tools marketing for Altera. ``Customers can now
quickly verify compliance of their designs with Altera's HDL coding
guidelines in order to optimize their implementation results and
reduce their design verification efforts. Combining LEDA's
capabilities with other tools such as Synopsys' FPGA Compiler II and
FPGA Express, opens new opportunities for designers to accelerate
their time-to-market.''
The Altera coding style policy for LEDA is comprised of a special
set of coding-style rules derived from the 300+ rules, pre-packaged
with Synopsys' LEDA programmable HDL checker. These rules check for
common mistakes and poor design practices such as treatment of module
inputs and outputs, resets, inadvertent inference of latches, gating
of clocks, etc. Altera determined these rules to be critical for
ensuring a smooth design flow and optimum performance when targeting
its PLD architectures. Synopsys also worked with Altera to customize
error-messages and documentation for these rules, thus giving
designers additional guidance for optimizing different tool-execution
options and selecting microarchitecture-level component.
``Since we released the Reuse Methodology Manual (RMM) and OpenMORE
guidelines with Mentor Graphics back in 1998, Synopsys has been
leading the EDA industry in providing design reuse solutions for ASIC
designers,'' said Steve Svoboda, director of marketing for LEDA
checkers at Synopsys. ``Now that PLDs have reached the
multimillion-gate level and have moved to an IP-based design paradigm,
we see a great opportunity to leverage for PLD designs, the design
reuse expertise we have gained for ASICs.''
Availability
The Altera Coding Style 1.0 policy will be available December 2000
and can be downloaded free of charge from the Synopsys web site to
current LEDA licensees.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View,
California, creates leading electronic design automation (EDA) tools
for the global electronics market. The company delivers advanced
design technologies and solutions to developers of complex integrated
circuits, electronic systems and systems on a chip. Synopsys also
provides consulting and support services to simplify the overall IC
design process and accelerate time to market for its customers. Visit
Synopsys at http://www.synopsys.com.
Synopsys and LEDA are registered trademarks of Synopsys, Inc. FPGA
Compiler II and FPGA Express are trademarks of Synopsys. Altera, APEX,
and Excalibur are trademarks and/or service marks of Altera
Corporation in the U.S. and other countries. All other trademarks or
registered trademarks mentioned in this release are the intellectual
property of their respective owners.
Contact:
Synopsys, Inc.
Meghan Le, 650/584-4832
meghan@synopsys.com
http://www.synopsys.com
or
KVO Public Relations
Judy Kahn, 650/919-2022
judy_kahn@kvo.com
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